Definitions

• APU
• FPU
• OPB
• PLB
• BRAM
• FCB
• EDK
• ISE
• ...

Why Does This HOWTO Exist?

Because no one else wrote one yet (I was unable to find some via Google). Xilinx provides documentation and example projects which leaves something to be desired. The documentation leaves out important information and warnings for newbies (such as how to check resource utilization, e.g. to resolve conflicts with over-utilization of BRAM). And the example projects - the examples I found just simply did not work. Also, discovering that the Xilinx Platform Cable USB did not work under Linux was a disappointment for me, and I just wanted to warn other people in advance (if I am wrong about this, please correct me).

To resolve these issues, I have clearly indicated what system I am using and what software versions I am using. If anyone uses this tutorial on a different version or platform, please let me know and I will update this document.

The Real Basics: Creating a New Project

How to create a new project using "Base System Builder:"

1. Open Xilinx Platform Studio ("xps" for short)

2. Create a new project and call it something like hello_fpu

3. Choose option "I would like to create a new design" (versus "I would like to load an existing .bsb file")

4. Choose your device:

   • Board vendor: Xilinx
   • Board name: Virtex 4 ML403 Evaluation Platform
   • Board revisions: 1

5. Now a "wizard" will be presented that allows the Virtex-4 to be configured with a variety of peripherals:

   1. FPGA:

      • Architecture: virtex4
      • Device: xc4vfx12
      • Package: ff668
      • Speed grade: -10

   2. Processor: PowerPC (versus MicroBlaze) (NOTE: the PowerPC is built-in to the Virtex-II Pro and Virtex-4 FX devices)

   3. Configure the PowerPC:

      • Reference clock frequency: 100 MHz
      • Processor clock frequency: 100 MHz (up to 300 MHz) (WARNING: the FPU can only operate up to 100 MHz [APU_FPU], therefore a clock divider/multiplier must be used if the CPU and FPU are running at different frequencies)
      • Debug I/F: JTAG
      • OCM Data: 0 kB (on-chip memory - uses "BRAM", see the note just a little further down the list about BRAM, and why this is currently set to 0)
      • OCM Instruction: 0 kB
      • Cache setup: Disable

   4. Configure other peripherals as desired (RS232_Uart, LEDs_4Bit, LEDs_Positions, DDR_SDRAM_64Mx32, Ethernet_MAC, SRAM_256Kx32, plb_bram_if_cntlr_1, and other peripherals such as OPB TIMER)

      • WARNING: When configuring plb_bram_if_cntrl_1, be conservative. Do not go above 64 kB (for the XC4VF12), otherwise the APU FPU might not fit into the FPGA fabric. This is because the amount of BRAM is limited. This size can be changed later if desired (how?).

   5. Set STDIN and STDOUT to RS232_Uart

   6. Enable sample applications (if desired):

      • Memory test
      • Peripheral selftest
      • For each program, use SRAM_256Kx32 for the Instruction, Data, and Stack/Heap sections. This can be changed later if desired (see sectionLinkerScript).

   7. Click "Generate" and then proceed to the next section of this document. (you are now finished creating a new project)

Adding the FPU to an Existing Project

This is explained in [APU_FPU], but for completeness, the steps are explained again here:

1. Find the IP Catalog and System Assembly View tabs (Have fun finding it! GUI's are so wonderful!)

2. Drag Arithmetic -> apu_fpu (version 2.10.a) from IP Catalog to System Assembly View

3. Drag Bus -> fcb_v10 (version 1.00.a) from IP Catalog to System Assembly View

4. Connect ppc405_0 and apu_fpu_0 to the FCB bus (by clicking the corresponding icons until they are solid)

5. In System Assembly View, switch to the "Ports" filter (this will show you what ports on each module are connected to which nets)

   • Connect to fcb_v10_0 FCB_CLK to sys_clk_s

   • Connect to fcb_v10_0 SYS_RST to sys_bus_reset

   • NOTE: Each of these settings corresponds to the MHS file (e.g. hello_fpu.mhs in this HOWTO). As such, you can either edit the MHS file, or you can use the System Assembly View GUI. Here's an example snippit from the MHS file (I have no idea why it says fcb_v10 here and fcb_v10_0 in the GUI - does it really matter?):

     BEGIN fcb_v10
      PARAMETER INSTANCE = fcb_v10_0
      PARAMETER HW_VER = 1.00.a
      PORT FCB_CLK = sys_clk_s
      PORT SYS_RST = sys_bus_reset
     END
     

   • NOTE: The FPU maximum clock is ~ 100 MHz. Make sure that the choice for FCB_CLK does not exceed this.

6. Switch the System Assembly View filter to Bus Interface. Edit the properties of ppc405_0 and set APU -> C_APU_CONTROL to 0b0000000000000001 (the original value is possibly 0b1101111000000000) (FIXME: what does this actually mean? link to docs?)

7. Check to make sure the design fits i7to the FPGA by compiling it:

   • Hardware -> Generate Netlist
   • Hardware -> Generate Bitstream
   • (if any the log window reports any errors caused by peripherals, such as Ethernet_MAC or DDR_SDRAM_64Mx32, perhaps consider removing that peripheral and then dealing with it later)

Writing the Program

Available and Utilized Resources

Performance

GCC Linker Script and BRAM

What's Happening on the Command Line?

Geeks Only: Linkage

''xps'' links to (according to ''ldd''):

ldd `which xps`
# >>>
linux-gate.so.1 =>  (0xffffe000)
libdl.so.2 => /lib/libdl.so.2 (0x40018000)
libpthread.so.0 => /lib/libpthread.so.0 (0x4001c000)
libstdc++.so.5 => /usr/lib/gcc-lib/i686-pc-linux-gnu/3.3.5-20050130/libstdc++.so.5 (0x4006e000)
libm.so.6 => /lib/libm.so.6 (0x40128000)
libgcc_s.so.1 => /usr/lib/gcc-lib/i686-pc-linux-gnu/3.3.5-20050130/libgcc_s.so.1 (0x4014b000)
libc.so.6 => /lib/libc.so.6 (0x40153000)
/lib/ld-linux.so.2 (0x40000000)

''ise'' is apparently staticly linked (good, I think: we don't have to worry about "Redhat syndrome"):

ldd `which ise`
# >>>
        not a dynamic executable